Description: verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,3-6章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 3-6 Platform: |
Size: 12288 |
Author:余月森 |
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Description: verilog hdl教程135例:verilog hdl语言类似于C语言,便于学习。本文档带有源代码,7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7- 8 Platform: |
Size: 8192 |
Author:余月森 |
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Description: Verilog HDL 程序
双路脉冲发生器的代码
包含了键盘控制,LED显示,脉冲发生,脉冲频率测量模块
是我自己写得,希望能对你有帮助,有问题可以mail:shaojunwu1@163.com-Verilog HDL dual-channel pulse generator procedure code includes a keyboard control, LED display, pulse, pulse frequency measurement module is written I hope to help you, it can be mail : shaojunwu1@163.com Platform: |
Size: 4096 |
Author:邵君武 |
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Description: CRC校验码,用于对数据流进行crc校验。
主要有CRC_16,CRC_8,CRC_32校验。
所用语言为Verilog HDL.-CRC code for the data flow crc check. Main CRC_16, CRC_8, CRC_32 check. The language used for Verilog HDL. Platform: |
Size: 10240 |
Author:李鹏 |
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Description: 键盘鼠标的原代码,用FPGA实现,使用Verilog HDL编写,已经使用FPGA验正过了,完全可以用-keyboard and mouse of the original code, using FPGA, using Verilog HDL preparation, already in use FPGA-mortem is over, it can be used Platform: |
Size: 1480704 |
Author:wpb3dm |
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Description: 经典计算机体系结构RISC8的源代码(Verilog),包括CPU、内存、寄存器等的实现-classic computer architecture RISC8 the source code (Verilog), including CPU, memory, such as the realization Register Platform: |
Size: 82944 |
Author:snake |
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Description: 本程序对如何使用altera系列芯片片上ram进行实例演示,采用Verilog HDL语言编写,并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序,值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit. Platform: |
Size: 180224 |
Author:panyouyu |
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Description: this Code is in verilog HDL.
This Code is for piplined processor with 4 opcode.
this will work in three cycle latch, decode and exicute..
test bench for xilinx ise is laos given
Platform: |
Size: 4096 |
Author:Yogesh PAtel |
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Description: ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no. -ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no. Platform: |
Size: 1024 |
Author:hassan |
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Description: 这是关于VERILOG HDL的有限状态机的源码,大家参考参考,应该有好处的。-This is about VERILOG HDL source code for finite state machines, we refer to the reference, it should be good. Platform: |
Size: 6126592 |
Author:罗啰 |
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